Present multi-layer semiconductor packaging techniques include multi-layer ceramic packages and multi-layer fiber-based packages. An example of a multi-layer ceramic package is shown in U.S. Pat. No. 4,972,253. Generally, in these multi-layer packages, several layers of non-conductive material (ceramic, fiber, resin, etc.) are laid up (laminated) with interleaved conductive wiring layers and power/ground planes, forming a mounting substrate and package for a semiconductor device (chip). The chip is mounted in an opening extending partially into the package (substrate) from an external surface thereof. These packages are sometimes referred to as "chip carriers".
In the case of multi-chip modules, two or more bare (unpackaged) chips may be mounted to a printed circuit board (PCB) substrate, typically to a multi-layer PCB having several levels of interconnects, and are eventually encapsulated or covered in some suitable manner.
The present invention relates primarily to chip carriers and multi-chip module substrates using several layers of printed circuit board material, namely "FR4" and "prepeg". "FR4" is a fibrous board material. "Prepeg" is essentially a flexible sheet of B-stage resin, or the like. One known prepeg material is BT resin.
Heat is inevitably generated during operation of a semiconductor device, and may become destructive of the device if left unabated. Modern semiconductor devices, operating at high speeds and with densely packed (i.e., small) transistor structures (e.g.) are particularly prone to heat-induced problems, such as outright device failure. Hence, one problem that must be addressed in virtually all modern semiconductor packaging schemes is providing a mechanism for conducting heat away from the operating semiconductor device. Previous techniques include the assembly of various discrete heat sink structures, slugs atop which the chip is mounted, thermally conductive vias extending through the package or substrate towards the reverse (non-circuit) side of the chip, and the like. The general overall object is to incorporate a thermally-conductive element close to the heat-generating die. However, the aforementioned approaches involve extra components and extra manufacturing steps, both of which add undesirable cost to the finished (i.e., packaged) device.
FIG. 1 shows a prior art technique 100 for packaging a semiconductor device. A multi-layer substrate 102 is fabricated of several (three shown) "core" layers 104, 106 and 108 of printed circuit board material, such as "FR4". These core layers typically contain a mat (or weave) of glass fiber, and a resin matrix. Interleaved between these core layers are layers of "prepeg" --a layer of prepeg 110 is disposed between the core layers 104 and 106, and a layer of prepeg 112 is disposed between the core layers 106 and 108. The layers 104, 106, 108, 110 and 112 are all of essentially the same overall dimension.
As shown in the example of FIG. 1:
The first, bottom-most (i.e., towards the legend "REAR") layer is a core layer 104 of generally planar (sheet-like) structure having a number of vias 112 extending completely therethrough in a central region thereof. PA1 The next higher (towards the legend "FRONT") layer is a planar prepeg layer 110, with no openings. PA1 The next higher layer is a core layer 106, which is also a planar structure, but which has a central opening 114 therethrough of sufficient dimension to accommodate a semiconductor device (DIE) 120 disposed in the opening 114, co-planar with the layer 106. The opening is about 0.050 to 0.100 inches larger than the die 120. In this manner, inner ends of wiring traces formed of a copper cladding (not shown) atop (towards "FRONT" legend) the prepeg layer 110 are exposed in the opening 114 for connection (e.g., wire bonding) to the semiconductor device 120. PA1 The next higher layer is another layer of prepeg 112 having a central opening 116 therethrough of dimension slightly (about 0.050 to 0.100 inches) larger than the opening 114 in the next lower layer 106. In this manner, inner ends of wiring traces formed of a copper cladding (not shown) atop (towards "FRONT" legend) the core layer 106 are exposed in the opening 116 for connection (e.g., wire bonding) to the semiconductor device 120. (Having two levels of wiring traces is not uncommon.) PA1 The next higher, top-most layer is another core layer 108 having a central opening 118 therethrough of dimension substantially (e.g., 0.100 to 0.200 inches) larger than either of the previous openings 114 and 116. In this manner, a shelf is formed on the front surface of the inner edge of the next lower prepeg layer 112, upon which a lid 130 is ultimately disposed to seal the die 120 within the package body formed by the substrate 102.
As shown in FIG. 1, an array of pins 140 extend normally (i.e., at ninety degrees) from the front surface of the top layer 108. As is known, these pins extend through various layers and make connection to the wiring traces and/or power and ground planes within the laminated substrate.
As is known, a plurality of bond wires 122 are connected between pads 124 on the front (active element) surface of the die 120 to the inner ends of wiring traces on the various levels of the substrate.
In use, the entire packaged semiconductor device is inserted by its pins 140 into a socket, or into aligned holes on a printed wiring board.